Assembly for 3d circuit with superposed transistor levels

ABSTRACT

Fabrication of a circuit with superposed transistors, comprising assembly of a structure comprising transistors formed from a first semiconducting layer with a support (100) provided with a second semiconducting layer (102) in which transistors are provided on a higher level (N2), the second semiconducting layer (102) being coated with a thin layer (101) of silicon oxide, the assembly of said structure and the support (100) being made by direct bonding in which the thin silicon oxide layer (101) is bonded to oxidised portions (37b, 37c) of getter material.

TECHNICAL DOMAIN AND PRIOR ART

This application relates to the field of integrated circuits containingcomponents distributed on several levels, and particularly superposedtransistors. Such devices are usually qualified as being 3-dimensionalor “3D” integrated circuits.

It aims particularly at implementation of a 3D circuit with an upperstage of transistors provided with back control electrode(s) acting asback gate or a ground plane.

In general, in the field of integrated circuits, there is an ongoingattempt to increase the density of transistors.

One solution to achieve this consists of distributing transistors onseveral levels of semiconducting layers positioned on top of each other.

Such circuits thus generally have a lower level provided with a firstsemiconducting layer starting from which the transistors are formed andat least one upper layer provided with at least one secondsemiconducting layer from which transistors are formed, the first andsecond semiconducting layers being superposed and separated from eachother by at least one insulating layer.

The “A 14 nm Finfet Transistor-level 3D partitioning Design to EnableHigh Performance and Low-Cost Monolithic 3D IC” document by Shi et al.,IEDM 2016 presents an example of a 3D circuit.

Production of the circuit can involve the use of a assembly step bybonding between a lower level in which transistors have already beenmade and a support in which the semiconducting layer of a higher levelis integrated.

Assembly between the support and the lower level is generally made bydirect bonding, in other words without needing to provide anyintermediate glue, typically between a silicon oxide layer of thesupport and an oxide layer formed on the lower level.

Such bonding may require a heat treatment. However, an excessively hightemperature can induce degradation of the lower level(s) andparticularly deterioration of the material of the contacts in the lowerlevel or inter-level connection elements or even accidental diffusion ofdopants within the lower level.

Therefore, one objective is generally to limit the thermal budget forbonding. In particular, it might be required to use heat treatments withtemperatures higher than 550° C.

However, under some conditions, particularly when the oxide layers arethin and the bonding temperature is low, and particularly less than 550°C., a hydrogen degassing phenomenon can occur and generate bondingdefects.

In some cases, molecular bonding can also cause untimely oxidation ofthe upper level semiconducting layer located in the support.

Therefore in particular the problem arises of finding a new method ofmaking a circuit with superposed transistors that is better with regardto the disadvantages mentioned above.

PRESENTATION OF THE INVENTION

According to one aspect, this application relates to a method of makinga circuit with superposed transistors comprising steps to:

a) provide a structure comprising at least one lower level of one orseveral transistors with a channel region formed in a firstsemiconducting layer supported on a substrate, said transistors beingcovered with at least one insulating layer in which one or severalconnection elements are formed, said structure being coated with one orseveral areas made of a given oxygen getter material capable ofoxidising,

b) assemble said structure with a support provided with at least onesecond semiconducting layer in which one or several channels of one orseveral higher level transistors are provided, the second semiconductinglayer being coated with a thin layer of silicon oxide, the assembly ofsaid structure and the support being made by bonding in which the thinsilicon oxide layer is bonded to oxidised portions of said one orseveral areas of said given oxygen getter material.

The bonding is typically called direct bonding.

The area(s) of getter material may be oxidised before an annealing stepunder an oxidising atmosphere or can oxidise during a annealing stepthat is conducted to consolidate a bonding interface between thestructure and the support.

In both cases, the area(s) of a given getter material act as oxygenabsorbing elements and participate in producing a stronger bondinginterface with fewer defects. If there is no oxygen getter, the degassedhydrogen could possibly react with available oxygen atoms and form —OHgroups that migrate to the surface less quickly than hydrogen. Inparticular, these —OH groups may be concentrated at the bondinginterface, particularly when the thermal budget is reduced, and createbonding defects.

The areas(s) of given getter material may also prevent or limit untimelyoxidation of the support.

The given oxygen getter material may for example be Ti, orunhydrogenated Si, or Mo, or Ru. Such materials make it possible to formstable oxides that can create chemical bonds with the thin oxide layerand thus create good bond on this thin oxide layer.

It is thus possible to have a bonding interface comprising oxidisedportions based on TiOx or TiO₂, or SiO₂, or MoO₂, or RuO₂.

Said one or several areas of a given oxygen getter material that canoxidise can be located on one or several conducting regionsrespectively, said conducting regions themselves being located on saidone or several connection elements, respectively.

Advantageously, at least a first conducting region among said conductingregions may form a control electrode of the channel of a giventransistor in said upper level or a ground plane of said giventransistor.

The first conducting region forming a control electrode can thus becoupled by electrostatic or capacitive coupling to the secondsemiconducting layer. Such a layout typically requires a supportprovided with a thin layer of silicon oxide, for example less than 20 nmthick. Despite the thinness of this layer, the areas(s) of gettermaterial assure that there are no bonding defects due to degassingphenomena.

Advantageously, according to a possible embodiment of the method, atleast one first conducting region among said conducting regions forms acontrol electrode of the channel given of a given transistor in saidupper level and is made on a first connection element, the firstconducting region comprising a first stack of metallic layers, saidfirst stack being coated with an area based on said given oxygen gettermaterial, at least one second conducting region among said conductingregions being made on another connection element and formed from asecond stack of metallic layers different from said first stack, saidsecond stack being coated with another area based on said given oxygengetter material. This second conducting region can advantageously formanother control electrode of the channel of another transistor in saidupper level.

A first conducting region can thus be provided with a first output workand a second conducting region can be provided with a second outputwork. This makes it possible to have transistors with differentthreshold voltages between the given transistor for which the channel isconnected to the first conducting region and the other transistor forwhich the channel is connected to the second conducting region, for thesame biasing and similar configurations.

In step a), said structure can advantageously be provided with severalconducting regions, each coated with an area based on an oxygen gettermaterial.

Said conducting regions can advantageously be separated from each otherby at least one silicon oxide block. This silicon oxide block can bemade before bonding the structure and the support. Such an arrangementmakes it possible to avoid the necessity to make STI type isolationtrenches and therefore the need to make trenches between higher leveltransistors that would be prolonged between subjacent controlelectrodes.

In this case, the structure and the support are also assembled bybonding between the thin layer of silicon oxide and the silicon oxideblock. The silicon oxide block can also be distributed around conductingregions.

According to one particular embodiment, the silicon oxide block can bemade by:

-   -   formation of a trench between a first conducting region and a        second conducting region among said conducting regions,    -   fill said trench with at least one layer of silicon oxide,    -   planarise said layer of silicon oxide. In this case, areas of        getter material and the oxide block produced are approximately        at the same height, which can improve the bond with the support.

Advantageously, when this oxide block is made and before said siliconoxide layer is made, a layer of dielectric material is formed that actsas a barrier to the diffusion of copper coating the bottom and the sidewalls of said trench.

According to one particular embodiment, said insulating layer in whichsaid one or several connection elements are formed may comprise asurface layer made of silicon oxide that can also be bonded to said thinlayer of silicon oxide during said assembly of the support and thestructure by bonding.

Each of said connection elements may comprise an upper end portionpassing through said surface layer made of silicon oxide. In this case,production of said conducting regions coated with areas made of anoxygen getter material can include steps to:

-   -   remove said end portions so as to form holes in the surface        layer exposing remaining portions of said connection elements,        then    -   formation of conducting regions and then areas of a given oxygen        getter material in the holes. Such a variant forms conducting        regions connected with connection elements in the lower level,        in a self-aligned manner.

According to one particular embodiment, at least one given connectionelement among said connection elements is based on copper. In this case,at least one of said conducting regions can be provided with aconducting layer forming a barrier to diffusion of copper in contactwith said copper connection element.

According to another aspect, one embodiment of this invention relates toa device with superposed transistors comprising: at least one lowerlevel of one or several transistors with a channel region formed in afirst semiconducting layer supported on a substrate, said lower leveltransistors being covered with at least one insulating layer in whichone or several connection elements are formed and that are connected toone or several conducting regions respectively, the conducting regionsbeing coated with one or several oxide layers respectively, made of agiven oxidised oxygen getter material, particularly such as TiO₂, orMoO₂, or RuO₂, or SiO₂, said oxide areas being assembled with a thinlayer of silicon oxide of a support provided with at least one secondsemiconducting layer in which one or several channels of one or severaltransistors respectively of a higher level is (are) formed, the thinsilicon oxide layer being coated with the second semiconducting layer,at least one first conducting region among said conducting regionsforming a channel control electrode or forming a ground plane of a givenhigher level transistor, the channel of which extends in the secondsemiconducting layer.

Advantageously, the first conducting region is coated with an insulatingstack formed from an oxide layer among said oxide areas made of a givenoxidised oxygen getter material, and a thin layer of silicon oxide, thethickness and the composition of the isolating stack being designed toenable electrostatic coupling between the first conducting region andthe channel of said given transistor.

According to one embodiment, the first conducting region can beconnected to a copper-based connection element. In this case, the firstconducting region is advantageously provided with a conducting layerforming a barrier to diffusion in contact with said given copperconnection element.

According to one particular embodiment, the copper-based connectionelement can be formed from a conducting line connected to anotherconducting line through a vertical conducting element also called a via.In this case, the copper-based connection element can be surrounded by abarrier to diffusion of copper.

Advantageously, the first conducting region can itself be surrounded bya layer of dielectric material forming a diffusion barrier.

According to one particular embodiment of the device, said conductingregions include: a first conducting region formed from a stack ofmetallic layers and at least one second conducting region in positionformed from another stack of metallic layers. With such an arrangement,it is possible to have transistors coupled to the first and secondregions respectively, with different threshold voltages, possible forthe same biaising.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention will be better understood after reading the descriptionof example embodiments given purely for information and in no waylimitative with reference to the appended drawings on which:

FIG. 1 illustrates an example of one possible initial structure for theuse of a device with several superposed component levels according to afirst embodiment of this invention;

FIG. 2A illustrates another example of a possible starting structurefrom which a method according to a first embodiment of the invention maybe implemented;

FIGS. 2B-2H illustrate an example of a method according to theinvention, in which areas of oxygen getter material, once oxidised,enable better bonding between a structure and a support each comprisinga semiconducting host level on which electronic components may beinstalled;

FIG. 3 illustrates an example of a superposed transistors device makinguse of a method according to the invention, the device being providedwith a higher level with one or several transistors comprising a gateelectrode and a back control electrode;

FIGS. 4A-4F illustrate an example variant of the method according to theinvention;

Identical, similar or equivalent parts of the different figures have thesame numeric references to facilitate the comparison between differentfigures.

The different parts shown on the figures are not necessarily all at thesame scale, to make the figures more easily understandable.

Furthermore, in the following description, terms that are dependent onthe orientation of the structure such as “on”, “below”, “above”,“vertical”, “horizontal”, “lower”, “upper” should be understood assumingthat the structure is oriented as shown in the figures.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

Refer to FIG. 1 that illustrates a possible initial structure for amethod according to the invention.

This structure comprises a substrate 10 on which at least one level N₁provided with one or several electronic components, particularlytransistors T₁₁, T₁₂, has been formed.

The transistors T₁₁, T₁₂ have a channel region arranged in a firstsemiconducting layer 11 and can be used on a bulk substrate 10 or on asemiconductor on insulator type substrate, and particularly on a SOI“Silicon On Insulator” type substrate, advantageously using the FDSOI(“Fully Depleted Silicon On Insulator”) technology.

The transistors T₁₁, T₁₂ are covered with at least one insulating layer13 in which one or several through conducting elements 14 a, 14 b, 14 cconnected to the transistor(s) are at least partially formed.

An interconnection elements stage 22 a, 22 b, 22 c passing through atleast one insulating layer is typically formed on transistors level N₁.

One manner of fabricating such interconnection elements 22 a, 22 b, 22 cis to use a “Back-end-of line” (BEOL) type method, particularly using aDamascene or double-Damascene technique. In this case, theinterconnection elements 22 a, 22 b, 22 c can be made of copper andformed in trenches coated with a copper diffusion barrier 21. Such abarrier 21 is typically formed from a stack of Ti/TiN or Ta/TaN. It isthus possible to make a copper diffusion barrier encapsulation below andlaterally using this stack. Another example of a material that can beused for the interconnection elements 22 a, 22 b, 22 c is Ru.

As a variant, the interconnection elements 22 a, 22 b, 22 c can be madeof W or Co. In this case, the diffusion barrier layer may be optional.

In the particular example illustrated on FIG. 2A, a connection element22 b is formed from a lower conducting line 18, typically horizontal orapproximately horizontal, arranged in an insulating layer 15, forexample made of SiOCN, this row 18 possibly being encapsulated laterallyby a conducting diffusion barrier 21 for example formed in a Ti/TiN orTa/TaN stack and on top by a dielectric barrier layer 16, for examplemade of SiN. A vertical conducting element 19 also called a “via”passing through the dielectric barrier layer 16 connects the lowerconducting line 18 to a higher conducting line 20, typically horizontalor approximately horizontal, and made in an insulating layer 17, forexample made of SiOCN. Filling of the trenches passing through theinsulating layer(s) can be followed by a CMP (“Chemical mechanicalplanarization”) polishing step. The result obtained is thus a structureof the type illustrated on FIG. 2A. This structure can also be used as apossible initial structure for use of a method according to theinvention.

The next step is to make one or several conducting regionsadvantageously designed to form one or several electrodes called the“back” control or ground plane electrodes of one or several transistorson a higher level at the previously formed level N₁.

To achieve this, a stack of conducting layers 31, 33, 35 is formed. Thestack preferably comprises a conducting layer 31 arranged directly onconnection elements 22 a, 22 b, 22 c, in other words in contact withthese elements. In the particular example embodiment illustrated on FIG.2B, when the connection elements are made of copper, this conductinglayer 31 is a copper diffusion barrier layer covering connectionelements 22 a, 22 b, 22 c. The barrier layer 31 is for example formedfrom a stack of Ti and TiN. The thickness of the barrier layer 31 mayfor example be between 3 and 10 nm. A layer 33 composed of a metallicmaterial is then deposited. In the illustrated example, the layer 33composed of a metallic material is a “solid plate”, in other words itcovers the entire upper face of the initial structure. The metallicmaterial is chosen as a function of the output work to be assigned tothe “back” electrodes. The layer 33 of metallic material can for examplebe based on TiN or TaN or W and its thickness may for example be between3 and 15 nm.

On some local parts, the stack may advantageously comprise an additionalconducting layer 35. In the example embodiment illustrated, theconducting layer 35 is an additional metallic layer that extends facingone or several connection elements 22 a, 22 b, but not facing theconnection element 22 c. The material of the conducting layer 35 ischosen as a function of the output work to be assigned to at least oneparticular “back” electrode. Different output work can then be obtainedfor an electrode that will be formed in the stack of layers 31, 33, andfor another electrode that will be formed in the stack of layers 31, 33,35, and therefore comprising this additional layer to adjust the outputwork. A conducting layer 35 based on TiN or TaN or W with a thicknessthat may for example be between 3 and 15 nm can be provided.

The stack of layers 31, 33, 35 is then coated with a surface layer 37made of an oxygen trapping material 38 that can oxidise.

In other words, the material 38 is an oxygen getter material that canoxidise. The material 38 is preferably a material that, when it is inthe oxidised form, can have a large adhesion capacity with a siliconoxide layer that can be formed later. For example, the material 38 canbe based on titanium, or non-hydrogenated amorphous silicon ormolybdenum or ruthenium. Typically, the thickness of the material 38 ischosen, particularly as a function of the solubility of oxygen in thematerial.

For example, when the getter material 38 is Ti, it can be consideredthat the theoretical solubility of oxygen in the Ti is for example ofthe order of 33%. Generally, direct bonding is done using a hydrophilicpreparation and is accompanied by the adsorption of some monolayers ofwater that produce a non-stoichiometric oxide TiOx. The preparation stepenables the formation of oxide and may include a CMP or plasmaactivation step or an ozone UV exposure step.

If it is required to obtain a TiOx layer of the order of 2 nm thick, athickness of material 38 for example equal to the order of at least 10nm thick can be chosen. This value takes account of a case in which thearea of oxidised getter material would occupy the entire surface that isto be bonded later with a support. However, the thickness of material 38chosen might also depend on the ratio of the area that this material 38will occupy in the bonding interface that will be made later.

According to a subsequent step illustrated on FIG. 1C, the superpositionof layers 31, 33, 35, 37 is etched so as to form distinct blocks 40 b,40 c and thus define distinct back electrodes.

On a first connection element 22 b, a first block 40 b is thus formedcomprising a stack of a first conducting region 34 b coated with a firstarea 37 b made of an oxygen trapping material 38 on this firstconducting region 34 b. On a second connection element 22 c, a secondblock 40 c is formed comprising a stack of a second conducting region 34c coated with a second area 37 c made of an oxygen trapping material 38on this second conducting region 34 b.

An insulating area is then formed between distinct blocks 40 b, 40 c andalso preferably around the blocks 40 b, 40 c, in order to form at leastelectrical insulation between the back electrodes, insulation aroundthese electrodes also being possible.

The insulating area can also be made as shown in the example in FIG. 2Dby deposition of a stack of layers 51, 52 made of dielectric materials.

A dielectric layer 51, that can be made by conforming deposition, isdeposited first. The dielectric layer 51 can be made of a materialcapable of forming a copper diffusion barrier, for example such as SiCN.The thickness of this dielectric layer 51 may for example by of theorder of 15 nm.

A trench is then filled between blocks 40 b, 40 c by a layer 52 made ofanother dielectric material chosen so that it can act as a bondingmaterial ready for subsequent assembly of the structure with anothersupport. The envisaged bonding is direct bonding. The layer 52 istypically made of silicon oxide. The thickness of this dielectric layer52 may for example by of the order of 20 nm or less.

As suggested previously, the thickness of the material 38 formed in theblocks 40 b, 40 c is also preferably chosen as a function of the ratioof the area that this material 38 will occupy to the total area of thebonding interface.

When a structure covered with getter material blocks and oxide blocks isbonded, allowance is made for the ratio of the area occupied by thegetter material to the total area including the getter material blocksand the oxide blocks. For example, considering a getter material 38 madeof Ti in which the ratio of the area occupied by this material 38 to thetotal area of the bonding interface also composed of 50% of the SiO₂layer 52 is equal to 50%, a thickness of material 38 equal for exampleto the order of 20 nm can be provided.

The thickness of material 38 can also be chosen as a function of thedistribution of blocks and more particularly the spacing between them.

The dielectric layers 51, 52 are then planarised, for example by CMP, soas to obtain insulating areas 53 between and around the blocks 40 b, 40c and with the same height as these blocks 40 b, 40 c (FIG. 2E).

The result obtained is thus an upper face that is plane or has littlerelief so as to facilitate subsequent assembly by direct bonding with asupport 100.

Such an assembly by direct bonding is illustrated for example on FIGS.2F-2G.

The support 100 that is transferred onto the previously made structureis coated with a thin layer of dielectric oxide 101. The support is alsoprovided with at least one semiconducting layer 102 from which an uppertransistor level is made. The thickness of the semiconducting layer 102of the support 100 may for example be between several nanometres 50 nmand 50 nanometres. Typically, the semiconducting layer 102 of thesupport 100 is arranged on one or several layers 103, 104, in particularwith an etching stop layer 103 for example made of silicon oxide and athick mechanical support layer 104 made for example of silicon.

The thin dielectric oxide layer 101 may be thin enough so thatelectrostatic coupling (also called capacitive coupling) can beestablished later between the semiconducting layer 102 and one orseveral previously formed back electrodes. The thin dielectric oxidelayer 101 is advantageously a thermal oxide layer typically based onsilicon oxide with a thickness that may be less than 20 nm, for examplebetween 10 and 20 nm.

Advantageously, a waiting time can be included between hydrophilicpreparation in view of bonding and the thermal annealing step. Such awaiting time, for example of the order of several tens of minutes ormore than an hour, and that can be adapted depending on the spacingbetween the different blocks 40 a, 40 b, can give the water moleculesthat move freely at a velocity for example of the order of 160 μm/hsufficient time to distribute in the different blocks 40 a, 40 b.

Assembly by direct bonding typically comprises thermal annealing at atemperature for example between 200° C. and 550° C., for a duration thatmay for example be of the order of one hour. In this example, annealingis done under an oxidising atmosphere. The blocks 40 b, 40 c coated withan oxygen trapping material 38 absorb oxygen and are superficiallyoxidised.

The result is thus that oxidised portions 37′b, 37′c are formed thathave good adhesion with the dielectric oxide 101.

Oxidation prior to thermal annealing is also possible. Thermal annealingcan then reinforce adhesion.

The insulating areas 53 formed around the blocks 40 a, 40 b coated withoxidised portions 37′b, 37′c also bond to the dielectric oxide 101 whenthey are made of silicon oxide and can thus participate in bonding.

Once the assembly is complete, the next step is to remove the layers103, 104 of the support when they are present, for example using etchingand planarisation (CMP) steps and so as to expose the semiconductinglayer 102 from which one or several transistors can be formed (FIG. 2H).

Thus, steps are then typically performed to form active areas in thesemiconducting layer 102, and then on this semiconducting layer 102 ofelectrodes of transistor gates on a higher level N₂, then contactelements.

In the example illustrated on FIG. 3, distinct semiconducting portions102 a, 102 b are formed from the semiconducting layer 102 transferred tothe lower layer N₁ of transistors. A transistor channel T₂₁ is providedin a first semiconducting portion 102 a, while there is a channel ofanother transistor T₂₂ in another semiconducting portion 102 b,separated from the first portion 102 a. In the particular exampleillustrated, different types of transistors T₂₁, T₂₂ are made, andparticularly transistors with different gate and channel structures. Thetransistor T₂₁ has a surrounding gate structure 106 a covering the upperface and the side faces of a semiconducting portion 102 a in the form ofa fin. The transistor T₂₂ has a structure with a plane gate 106 blocated on the semiconducting portion 102 b. The gates 106 a, 106 b canfor example be formed from a stack of polysilicon and TiN on a gatedielectric formed from a stack of HfO₂ and SiO_(x).

The transistors T₂₁ and T₂₂ can be isolated from each other by a Shallowtrench isolation (“STI”) type isolation, or preferably of a typecommonly called “mesa”, in other words without making trenches under thetransistors.

The conducting regions 34 b, 34 c located underneath the channel regionof the first transistor T₂₁ and under the channel region of the othertransistor T₂₂ respectively can be coupled by capacitive orelectrostatic coupling to these channel regions and can thus formaddition control regions for these channel regions. The possibility ofsetting up such coupling depends on the composition and thickness of aninsulating stack separating each conducting region 34 a (or 34 b) fromthe semiconducting channel portion 102 a (or 102 b respectively) facingit.

In other words, it depends particularly on the thickness and compositionof the thin layer of silicon oxide 101 and the thickness and compositionof the area of oxidised getter material located under the semiconductingportions 102 a, 102 b.

The transistors T₂₁, T₂₂ are covered with at least one insulating layer113 in which one or several conducting elements 114 b, 114 c, 114 d, 114e are made. A conducting element 114 a can be used to make contact withthe interconnection level arranged on the lower level N₁ of transistors,while conducting elements 114 c, 114 d, 114 e can be used to makecontact with transistors T₂₁ and T₂₂ on the higher level N₂. In theexample illustrated, a conducting element 114 b makes contact on theconducting region 34 b forming a back electrode of the transistor T₂₁.

A variant embodiment will now be described with reference to FIGS.4A-4D.

The initial structure is similar to the structure described above withreference to FIG. 2A with connection elements 22 a, 22 b, 22 c formedabove the lower level N₁ of transistors. One end of these connectionelements 22 a, 22 b, 22 c is formed in a thickness of insulatingmaterial comprising a surface layer 17′, typically made of siliconoxide.

The next step is to remove end portions of connection elements 22 a, 22b, 22 c so as to form holes 23 a, 23 b, 23 c, in the insulatingthickness and particularly in the surface layer 17′. The holes 23 a, 23b, 23 c made expose the connection elements 22 a, 22 b, 22 c. Forexample, a thickness corresponding approximately to the depth of theholes 23 a, 23 b, 23 c can be removed, for example of the order ofseveral tens of nanometres.

Conducting regions are then formed in the holes 23 a, 23 b, 23 c, andwill be used to form back control electrodes.

These conducting regions are formed typically by making a stack ofconducting layers 31, 33, a copper diffusion barrier conducting layer 31being formed for example of Co or a stack of Ti and TiN and a layer 33made of a metallic material.

Different stacks can be used from one hole to another so as to be ableto make back control electrodes as described above, with differentcompositions for different transistors.

Thus, an additional conducting layer 35 is formed in one or severalholes 23 a, 23 b, this additional conducting layer 35 not being locatedin at least one other hole 23 c.

Such a selective filling can be made for example by masking 28, forexample based on resin or nitride, typically formed by photolithography,on parts of the structure on which it is required to make the additionallayer 35.

In the example illustrated on FIG. 4C, the hole 23 c is not protected bymasking 28, while other holes 23 a, 23 b are covered by masking 28.

The additional conducting layer 35 is then etched at unmasked parts. Themask 28 is then removed.

In this example embodiment, and since conducting regions are made inholes, when the connection elements 22 a, 22 b, 22 c are made of copper,the first conducting layer 31 of the stack forming the conductingregions can be sufficient to form a diffusion barrier. Thus, in thisexample, the diffusion barrier can be made by a metallic layer ratherthan by means of a layer of dielectric material.

FIG. 4D illustrates a later step in the formation of a layer of material38 capable of absorbing oxygen and oxidising on the structure. Someareas of oxygen getter material 38 are formed in holes 23 a, 23 b, 23 cand cover the different conducting regions 34 a, 34 b, 34 c made in theholes.

Planarisation (CMP) is then conducted to remove layers deposited aroundthe holes and projecting beyond the opening of the holes. To achievethis, the first step is to form an insulating layer 39, for examplesilicon oxide, as shown on FIG. 4E.

The conducting regions and the areas of getter material 38 cover theseregions are thus kept only in the holes 23 a, 23 b, 23 c.

After making the removal, the support 100 provided with the thin layerof dielectric oxide 101 used for bonding can be assembled with thesemiconducting layer 102 in which the transistor channels are provided(FIG. 4F).

1. A method of making a circuit with superposed transistors comprising:a) providing a structure comprising at least one lower level of one orseveral transistors with a channel region formed in a firstsemiconducting layer supported on a substrate, said transistors beingcovered with at least one insulating layer in which one or severalconnection elements are formed, said structure being coated with one orseveral zones made of a given oxygen getter material capable ofoxidising, b) assembling said structure with a support provided with atleast one second semiconducting layer in which one or several channelsof one or several higher level transistors are provided, the secondsemiconducting layer being coated with a thin layer of silicon oxide,particularly SiO₂, the assembly of said structure and the support beingmade by bonding, the thin silicon oxide layer being brought into contactwith and bonded to oxidised portions of said one or several areas ofsaid given oxygen getter material, so as to make a bonding interfacebetween portions of oxide of said given getter material and the thinsilicon oxide layer.
 2. The method according to claim 1, wherein saidgiven oxygen getter material is chosen from among the followingmaterials: non-hydrogenated Ti, Mo, Ru, Si.
 3. The method according toclaim 1, wherein said one or several areas of a given oxygen gettermaterial that can oxidise are located on one or several conductingregions respectively, said conducting regions themselves being locatedon said one or several connection elements, respectively, at least oneof said conducting regions forming a control electrode of the channel ofa given transistor in said upper level or a ground plane of said giventransistor.
 4. The method according to claim 1, wherein at least onefirst conducting region among said conducting regions forms a controlelectrode of the channel given of a given transistor in said upper leveland is made on a first connection element, the first conducting regioncomprising a first stack of metallic layers, said first stack beingcoated with an area based on said given oxygen getter material, at leastone second conducting region among said conducting regions being made onanother connection element and formed from a second stack of metalliclayers different from said first stack, said second stack being coatedwith another area based on said given oxygen getter material.
 5. Themethod according to claim 1, wherein in step a), said structure hasseveral conducting regions, each coated with an area based on an oxygengetter material, said conducting regions being separated from each otherby at least one block made of silicon oxide, particularly SiO₂, thestructure and the support also being assembled by bonding between thethin layer of silicon oxide and the silicon oxide block.
 6. The methodaccording to claim 5, wherein the production of said silicon oxide blockincludes the following steps: creation of a trench between a firstconducting region and a second conducting region among said conductingregions, fill said trench with at least one layer of silicon oxide,planarise said layer of silicon oxide.
 7. The method according to claim6, wherein before said silicon oxide layer is made, a layer ofdielectric material is formed that acts as a barrier to the diffusion ofcopper coating the bottom and the side walls of said trench.
 8. Themethod according to claim 1, wherein said insulating layer in which saidone or several connection elements are formed comprises a surface layermade of silicon oxide that can be bonded to said thin layer of siliconoxide during said assembly of the support and the structure by bonding,each of said connection elements comprises an upper end portion passingthrough said surface layer made of silicon oxide, the production of saidconducting regions coated with areas made of a given oxygen gettermaterial including steps to: remove said end portions so as to formholes in the surface layer exposing remaining portions of saidconnection elements, then formation of conducting regions and then areasof a given oxygen getter material in the holes.
 9. The method accordingto claim 1, wherein at least one given connection element among saidconnection elements is made of copper, at least one of said conductingregions comprising a conducting layer forming a barrier to diffusion ofcopper in contact with said copper connection element.
 10. The method ofmaking a circuit with superposed transistors comprising: a) providing astructure comprising at least one lower level of one or severaltransistors with a channel region formed in a first semiconducting layersupported on a substrate, said transistors being covered with at leastone insulating layer in which one or several connection elements areformed, said structure being coated with one or several zones made of agiven oxygen getter material capable of oxidising, b) assembling saidstructure with a support provided with at least one secondsemiconducting layer in which one or several channels of one or severalhigher level transistors are provided, the second semiconducting layerbeing coated with a thin layer of silicon oxide, particularly SiO₂,assembly of said structure and the support comprising the followingsteps: annealing under an oxidising atmosphere so as to form oxidisedportions of said one or several areas of said given oxygen gettermaterial, and bonding, in which the thin layer of silicon oxide isbonded to said oxidised portions, so as to make a bonding interfacebetween oxide portions of said give getter material and the thin layerof silicon oxide.
 11. The method according to claim 10, wherein saidgiven oxygen getter material is chosen from among the followingmaterials: non-hydrogenated Ti, Mo, Ru, Si.
 12. The method according toclaim 10, wherein said one or several areas of a given oxygen gettermaterial that can oxidise are located on one or several conductingregions respectively, said conducting regions themselves being locatedon said one or several connection elements, respectively, at least oneof first conducting regions forming a control electrode of the channelof a given transistor in said upper level or a ground plane of saidgiven transistor.
 13. The method according to claim 10, wherein at leastone first conducting region among said conducting regions forms acontrol electrode of the channel given of a given transistor in saidupper level and is made on a first connection element, the firstconducting region comprising a first stack of metallic layers, saidfirst stack being coated with an area based on said given oxygen gettermaterial, at least one second conducting region among said conductingregions being made on another connection element and formed from asecond stack of metallic layers different from said first stack, saidsecond stack being coated with another area based on said given oxygengetter material.
 14. The method according to claim 10, wherein at stepa), said structure is provided with several conducting regions, eachcoated with an area based on an oxygen getter material, said conductingregions being separated from each other by at least one block made ofsilicon oxide, particularly SiO₂, the structure and the support beingassembled by bonding between the thin layer of silicon oxide and thesilicon oxide block.
 15. The method according to claim 14, wherein theproduction of said silicon oxide block includes the following steps:creation of a trench between a first conducting region and a secondconducting region among said conducting regions, filling said trenchwith at least one layer of silicon oxide, planarising said layer ofsilicon oxide.
 16. The method according to claim 15, wherein before saidsilicon oxide layer is made, a layer of dielectric material is formedthat acts as a barrier to the diffusion of copper coating the bottom andthe side walls of said trench.
 17. The method according to claim 16,wherein said insulating layer in which said one or several connectionelements are formed comprises a surface layer made of silicon oxide thatcan also be bonded to said thin layer of silicon oxide during saidassembly of the support and the structure by bonding, each of saidconnection elements comprises an upper end portion passing through saidsurface layer made of silicon oxide, the production of said conductingregions coated with areas made of an oxygen getter material including:removing said end portions so as to form holes in the surface layerexposing remaining portions of said connection elements, then formingconducting regions and then areas of a given oxygen getter material inthe holes.
 18. The method according to claim 10, wherein at least onegiven connection element among said connection elements is made ofcopper, at least one of said conducting regions comprising a conductinglayer forming a barrier to diffusion of copper in contact with saidcopper connection element.